This invention relates to an MOS dynamic random access memory (RAM) device of the single transistor type in which the cell plate voltage is controlled by a word line signal to thereby obtain a large signal at high speed.
In general, in MOS dynamic RAMs of the single transistor type, the presence and absence of a charge accumulated on a MOS capacitor are related to the binary signals 1 and 0, respectively, and the accumulated charge on the MOS capacitor is transferred to a bit line by turning on a transfer gate. A small voltage variation generated on the bit line depending on the state of the charge is detected by a sensing amplifier circuit.
FIG. 1 shows a conventional array of MOS dynamic memories. In FIG. 1, memory cells 1 are arranged, in a matrix, in left and right halves of the array, respectively. FIG. 2 is a cross sectional illustration of one of the memory cells.
In FIG. 2, the memory cell 1 includes a bit line 4 of metal, a word line 5 of electrode material such as polysilicon, a memory capacitor cell plate 8, a gate oxide layer 10, a memory terminal 11 of an N-type region and a thick field oxide layer 12 for isolating adjacent memory cell, which are to be described later.
Returning to FIG. 1, memory cells are provided in each of the halves. A dummy cell 3 is provided for each bit line 4 of each line of the memory cells in each matrix half, and a sensing amplifier 2 is connected between each bit line 4 in one of the matrix halves and a corresponding bit line in other matrix half. A word line 5 is provided for each row of memory cells 1 in each matrix half and a dummy word line 6 is provided for each row of the dummy cells 3. The dummy cells 3 in each row are connected to a .phi..sub.p line 7 through which a .phi..sub.p signal is supplied. Cell plates 8 are provided for each matrix half for applying a memory capacity voltage V.sub.DD to the memory cells 1 and the dummy cells 3 in the matrix half.
In operation, when, for example, one of the word lines 5 in the left side of the matrix is selected, a right side dummy word line 6 connected to the dummy cell having half of the memory capacity is selected. Thus, a signal charge of the bit lines 4 in the left half is transferred to the corresponding bit lines 4 in the right half, and a small potential difference caused thereby is detected and amplified by the sensing amplifier 2.
In the conventional operation of the memory, the amount of the signal charge transferred to the bit line 4 when the word line voltage assumes the V.sub.DD level is C.sub.s (V.sub.DD -V.sub.T) where C.sub.s is the memory capacity and V.sub.T is the threshold voltage of the transfer gate. Further, when an RC component of the word line is large, the word line signal is delayed and the read-out speed at the terminal position is lowered, causing high speed operation to be impossible.